OpenServo.com

[guru]

Hi all,

I am working on an FPGA board with 400k or 1M gates. It will be able to run ucLinux and control all sensors and servos whether analog or digital.

It has the following features:
Xlinix XC3S400 or 1000 FPGA & XC95108 pair
32MB SDRAM
8MB FLASH
100MB Ethernet
FTDI USB2 Serial
RS232 Serial
IDE Interface
SD Card
BurrBrown PCM Audio Codec
8ch Analog to Digital Converter (not shown yet)
Lots of GP IO
FPGA, CPLD & XCF are accessible via JTAG port

Runs from a single Li-Ion or Li-Poly battery and contains a battery charger and supervisor. Voltages are 1.2v, 2.5v, 3.3v and -2.5v. All but +2.5v are switched.

The design is meant for many of my other projects, but is also perfect for robotics.

The board will run many of the soft processors on opencores.org and the Xilinx MicroBlaze. I am hoping to be able to optionally bootstrap the Xilinx FPGA from a file on an SD Card and also the SDRAM contents as well. So your fpga and linux images could easily be put on an sd card.

I am about 90% or more complete the schematics. It is still a work in progress!

The schematics are:
http://www.colinmackenzie.net/downloads/Schematics.pdf

A whole package containing altium and many of the chip docs are:
http://www.colinmackenzie.net/downloads/fpga-board.rar

Have a look, provide feedback. I would like to give this design to openservo.org. Perhaps mike can create another section for it. What can you do with servos without a host controller right?

Colin

[ginge]

Hi Colin,

Very nice! At least I know what those previous questions were all about

I am very impressed with your design, it leaves nothing out. I don't have any specific comments about the anything as yet, If I think of anything I will let you know.

Thanks for the contribution!

Barry
_________________
http://www.headfuzz.co.uk/
http://www.robotfuzz.co.uk/

[mpthompson]

[guru]

I have routed all the pins of the SDRAM to the FPGA, so splitting the mem into two banks is not a problem. There are 4 banks in this SDRAM.

I am glad to hear about your verilog motor controller with OPB bus as I am planning on providing prebuilt binaries for microblaze and uclinux. It would also be possible to select peripherals on a web site and have the web server built the binary for the user. That way, it gets around everyone requiring the Xilinx XDK and license. Most people will only want to download an already compiled binary for what they want anyway. Etherboot web site works this way.

C

[Cliff]

Hi Colin,

Looks like an interesting play ground your building.

You might find this app-note interesting: Xapp441. Using the ideas presented there, you could get rid of the Platform Flash (those things are expensive!) and instead use the system Flash and CPLD to configure the FPGA, and be able to change the system Flash (including FPGA image) via Ethernet. The design includes the notion of falling back to the last image if there is a load failure. The design files can be found here.
Also, with the above in place, it would be easy to extent the design to look on the SD port first for a configuration file and use that if it exists.

Here is a diagram from the App-note:

After configuration, the address lines from the CPLD could become inputs and with the addition of another select line, the Flash address and data buses could access registers in the CPLD, effectively memory mapping the registers.

A few random things I noticed and odd questions from looking at the schematics:

The 50MHz. clock is using series source termination, which is good, but not with multiple end points. You might want to run the clock into the CPLD and back out to the FPGA or consider using clock buffers. Another choice would be to use AC termination (47 Ohms in series with 47pF to ground) at the FPGA and CPLD clock inputs (and removing the source termination).

Xapp942 talks about OPB Ethernet MAC and notes that the Spartan 3 EMAC and MicroBlaze clock needs to be greater than 65MHz. in order to operate a link speed of 100 Mbps, otherwise, it can only support 10 Mbps mode. Are you using 2X the input clock from a DLL or something else using DFS?

Are you doing an I2C master in the CPLD or are those just bits to bang with the MicroBlaze? If I remember right, an I2C master is only about 70 CLBs in the FPGA, but would chew a very big hole in your CPLD.

On your triple supply you have 33M Ohm current sense resistors (Vin to IS1 and IS2), they should be [Edit] 0.033 Ohms. Also, you are missing the recommended bypass caps on the Vin end of those sense resistors (yes, I know they seem redundant, but leave them off or move them away from the resistors, at your peril!). BTW, Vin on your schematic, I believe should be Vbatt.

Also, I must be missing a schematic page - I don't see a bunch of I2C OpenServo ports anywhere!

Cliff

[guru]

I like that app note, thanks! I wanted to be able to store the xilinx image in regular flash but couldnt quite work out how I was going to do that. The regular flash was a recent addition to the design. I like the ethernet image upload too. This is like the x3 mod chips for the xbox that I use and like so much.

I didnt think about the clock problem. The 50MHz clock is for the CPLD, and then in the FPGA I was going to use the DCM modules to double it, or divide as necessary. The XC3S has 4 DCM modules. and can provide buffered 33M, 50M, 66M, and 100M clocks and many more from the 50MHz source. I guess the best thing would be to put the clock into the CPLD and have the CPLD buffer it and send it to the FPGA?

I dont know what DFS is, but you are right 2x clock using DCM (Digital Clock Module) inside the FPGA.

I was planning on doing the i2c as a master OPB peripheral. Didnt think about how much it would eat of the CPLD. The FPGA is intended for real I2C and the lines on the CPLD are really just GPIO.

I thought the 33m was odd on the reference design. I assumed megaohm...but i guess they meant milli, which would be 0.033 ohm. That makes more sense. I will add the caps too.

I would like to add the current sensor from the open servo design too, so the ADC will digitize the current draw from Vbatt. I dont think there is a need to put more on each regulator output except maybe on a regulator for external supply maybe. I am thinking on adding a 5v buck/boost too just for external use. Most people that use the board will probably want 5v. Comments?

You are missing a page! But I havent forgotten, all the GPIO can be used to make i2c busses for open servo. If there is an intellegent plug that can be used for GPIO and open servo ports I am all ears. I would rather not supply power to motors though unless through a dedicated 5v buck/boost, so the motors wouldnt corrupt my sensitive FPGA req's.

C

[Cliff]

Colin,

Thinking more about your 50 MHz. clock, I think the AC termination will give you the least phase difference between the FPGA and CPLD clocks. Ideally, the clock lines, from the oscillator, would both start at the oscillator pin and have close to the same lengths to the clock inputs.

[Cliff]

Colin,

[guru]

I have switched to AC termination on the clock. fyi, I only wanted a single clock oscillator for the reasons of phase difference too, all clocks should derive from a single clock. I am thinking of adding an extra oscillator unpopulated for the user. Rather than spend logic and latches dividing a 50MHz clock for the popularly used 37.5KHz or for a user interface clock it would be nice to just add a low speed clock oscillator.

I think the m was a 'me' thing, bad habit. I have started changing the m to u.

The current from the battery better be only running in one direction! Or chips will start frying. Do you have a suggested battery supervisor? I can go nuts reading so many datasheets and part searches trying to find the right fit.

I am changing the Flash ROM out for a higher density since the XCF Platform Flash will be removed. The XCS400 recommended the 4MB version, and the XCS1000 the 8MB XCF. Thus, an 8MB flash ROM isnt going to fit two fpga configs, some SRAM contents, and perhaps a file system! I am looking at the Intel Strata Flash 56-pin TSOP.Which has flash from 8MB to 64MB. Same Common Flash Interface CFI.

I will post some more later today.

Colin

[Cliff]

Colin,

The XC3S400 is 1,699,136 bits (212,392 Bytes) and the XC3S1000 is 3,223,488 bits (402,936 Bytes) - I think you must have thought Xilinx were talking Bytes not bits, because they are charging so much for their Platform Flash.

[guru]

I am wiring the fpga, cpld and flash together for the cpld programming the fpga as per the appnote you mentioned. It seems that I could wire it up so the fpga is programmed in parallel SelectMAP mode with perhaps less cpld resources.

The connection diagram in the appnote is still the same except that the selectMap D0-D7 pins are chosen to be the lower 8bits of FLASH_DQ[0:7]. Also note, the Din pin (same as selectmap D0 pin) is already connected.

The cpld sequences the Flash ROM. For each even address of the flash, the flash outputs its lower 8bits into the fpga selectMap D0-D7. The CPLD reads the higher 8 bits into a register. The odd cycles, the cpld outputs its 8 bit register onto the selectMap D0-D7 while deactivating the Flash PROM output enable.

Viola! Parallel programming of the fpga...much faster than serial.

To be safe, I may connect Din to cpld alone, then I can connect Din to Flash D0 inside the cpld if I use paralllel mode, and still be able to do serial programming mode without a Din/Flash DQ0 conflict. SelectMAP D1-D7 would still be routed to Flash DQ[1-7] as these select map pins are not used in serial mode.

Does this sound solid? ....Cliff?

C

[Cliff]

Colin,

I don't have any experience with the selectMap configuration mode (I never want give up the pins), but what you have outlined looks to me to be reasonable and doable. The additional upsides I can see (off the top of my head) are being able to do partial re-configuration and read back. However, to use these modes, the MicroBlaze would have to be in a mode of operation where it is not doing any Flash accesses (as the CPLD would need control) and the scheme would have to use the Flash as a data buffer. I'm sure there must be some downsides, but in this case I can't think of any that apply.

If you want the ability to do either parallel or serial configuration, there might be a case for having the CPLD control the FPGA's configuration mode pins.

BTW, you might want to add a soft JTAG interface to the FPGA (and JTAG connector) for use with the Altium version of ChipScope and related debug cores.

Cliff

[guru]

Thanks Cliff. Partial reconfiguration would be nice. I forgot about that. The microblaze shouldnt access the bus much if the instruction cache is enabled. But some thought would have to be done to insure a cache read into the instruction cache didnt occur in the middle of the operation. Could partial reconfiguration allow a design to be downloaded into the fpga over the ethernet?

I have spent hours looking for a header receptacle for 1.8" hard drives and the pin out. Do you know what header I could use so that I could mount a 1.8 inch hard drive directly to the FPGA board. Obviously right angled.

I have found out so far that the size of the connector is the same as the Compact Flash header and its 50 pins. I assume the pinout is the same as the ATA 50-pin connector for 2.5" hard drives only smaller. I have a Compact Flash to regular IDE adapter. I will check out the pinouts later tonight. The nice thing is that with the right header either a 1.8inch HD or Compact Flash could be used.

C

[guru]

btw: I also got the 5v boost supply implemented using an LTC1935 as well, and simulated using the Switcher CAD. It safely has about 500mA capacity from a 3.3v battery.

[Cliff]

Colin,

I found some information on 1.8 drive connectors, but it appears there is no standard connector. From Tom's Hardware site: